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<div class="title">xipipsu_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gaf92686c675ebd6fe4efc7213c7f8f204"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#gaf92686c675ebd6fe4efc7213c7f8f204">XIPIPSU_HW_H_</a></td></tr>
<tr class="memdesc:gaf92686c675ebd6fe4efc7213c7f8f204"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; prevent circular inclusions  <a href="group__ipipsu__api.html#gaf92686c675ebd6fe4efc7213c7f8f204">More...</a><br/></td></tr>
<tr class="separator:gaf92686c675ebd6fe4efc7213c7f8f204"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7c62207cd1bb028fe62103eee40477f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#ga7c62207cd1bb028fe62103eee40477f2">XIPIPSU_MSG_RAM_BASE</a>&#160;&#160;&#160;0xFF990000U</td></tr>
<tr class="memdesc:ga7c62207cd1bb028fe62103eee40477f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">IPI Message RAM base address.  <a href="group__ipipsu__api.html#ga7c62207cd1bb028fe62103eee40477f2">More...</a><br/></td></tr>
<tr class="separator:ga7c62207cd1bb028fe62103eee40477f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5989f697e24f79be32727d13ee3f4350"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#ga5989f697e24f79be32727d13ee3f4350">XIPIPSU_MSG_BUF_SIZE</a>&#160;&#160;&#160;8U</td></tr>
<tr class="memdesc:ga5989f697e24f79be32727d13ee3f4350"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer size for up to 8 messages, each 4-bytes long.  <a href="group__ipipsu__api.html#ga5989f697e24f79be32727d13ee3f4350">More...</a><br/></td></tr>
<tr class="separator:ga5989f697e24f79be32727d13ee3f4350"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6677575d97c6c8df0a1776fdbd94b7e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#gad6677575d97c6c8df0a1776fdbd94b7e">XIPIPSU_MAX_BUFF_INDEX</a>&#160;&#160;&#160;7U</td></tr>
<tr class="memdesc:gad6677575d97c6c8df0a1776fdbd94b7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum Buffer Index.  <a href="group__ipipsu__api.html#gad6677575d97c6c8df0a1776fdbd94b7e">More...</a><br/></td></tr>
<tr class="separator:gad6677575d97c6c8df0a1776fdbd94b7e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae0907003c35118f6135e65877227d15e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#gae0907003c35118f6135e65877227d15e">XIPIPSU_BUFFER_OFFSET_GROUP</a>&#160;&#160;&#160;(8U * 2U * 32U)</td></tr>
<tr class="memdesc:gae0907003c35118f6135e65877227d15e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer offset for group.  <a href="group__ipipsu__api.html#gae0907003c35118f6135e65877227d15e">More...</a><br/></td></tr>
<tr class="separator:gae0907003c35118f6135e65877227d15e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1b15715fa2640ed4fd66146d328bbbba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#ga1b15715fa2640ed4fd66146d328bbbba">XIPIPSU_BUFFER_OFFSET_TARGET</a>&#160;&#160;&#160;(32U * 2U)</td></tr>
<tr class="memdesc:ga1b15715fa2640ed4fd66146d328bbbba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer offset for target.  <a href="group__ipipsu__api.html#ga1b15715fa2640ed4fd66146d328bbbba">More...</a><br/></td></tr>
<tr class="separator:ga1b15715fa2640ed4fd66146d328bbbba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2361ea49ab17d6cc10e53ea607a9e9f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#gaf2361ea49ab17d6cc10e53ea607a9e9f">XIPIPSU_BUFFER_OFFSET_RESPONSE</a>&#160;&#160;&#160;(32U)</td></tr>
<tr class="memdesc:gaf2361ea49ab17d6cc10e53ea607a9e9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Buffer offset for response.  <a href="group__ipipsu__api.html#gaf2361ea49ab17d6cc10e53ea607a9e9f">More...</a><br/></td></tr>
<tr class="separator:gaf2361ea49ab17d6cc10e53ea607a9e9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga47ff7fda69269789f8a32d6be7357712"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#ga47ff7fda69269789f8a32d6be7357712">XIPIPSU_MAX_TARGETS</a>&#160;&#160;&#160;XPAR_XIPIPSU_NUM_TARGETS</td></tr>
<tr class="memdesc:ga47ff7fda69269789f8a32d6be7357712"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum number of targets.  <a href="group__ipipsu__api.html#ga47ff7fda69269789f8a32d6be7357712">More...</a><br/></td></tr>
<tr class="separator:ga47ff7fda69269789f8a32d6be7357712"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7b5daa2f9a7fef0e3897606b491dafcc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#ga7b5daa2f9a7fef0e3897606b491dafcc">XIPIPSU_TRIG_OFFSET</a>&#160;&#160;&#160;0x00U</td></tr>
<tr class="memdesc:ga7b5daa2f9a7fef0e3897606b491dafcc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset for Trigger register.  <a href="group__ipipsu__api.html#ga7b5daa2f9a7fef0e3897606b491dafcc">More...</a><br/></td></tr>
<tr class="separator:ga7b5daa2f9a7fef0e3897606b491dafcc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ca8515703f72eb2194a408cfa5b4a18"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#ga1ca8515703f72eb2194a408cfa5b4a18">XIPIPSU_OBS_OFFSET</a>&#160;&#160;&#160;0x04U</td></tr>
<tr class="memdesc:ga1ca8515703f72eb2194a408cfa5b4a18"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset for Observation register.  <a href="group__ipipsu__api.html#ga1ca8515703f72eb2194a408cfa5b4a18">More...</a><br/></td></tr>
<tr class="separator:ga1ca8515703f72eb2194a408cfa5b4a18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c9abd1d0247d6b28268131d90b62a05"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#ga5c9abd1d0247d6b28268131d90b62a05">XIPIPSU_ISR_OFFSET</a>&#160;&#160;&#160;0x10U</td></tr>
<tr class="memdesc:ga5c9abd1d0247d6b28268131d90b62a05"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset for ISR register.  <a href="group__ipipsu__api.html#ga5c9abd1d0247d6b28268131d90b62a05">More...</a><br/></td></tr>
<tr class="separator:ga5c9abd1d0247d6b28268131d90b62a05"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga44ee4ca145f4adbe7584e6d9a08c4bdf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#ga44ee4ca145f4adbe7584e6d9a08c4bdf">XIPIPSU_IMR_OFFSET</a>&#160;&#160;&#160;0x14U</td></tr>
<tr class="memdesc:ga44ee4ca145f4adbe7584e6d9a08c4bdf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset for Interrupt Mask Register.  <a href="group__ipipsu__api.html#ga44ee4ca145f4adbe7584e6d9a08c4bdf">More...</a><br/></td></tr>
<tr class="separator:ga44ee4ca145f4adbe7584e6d9a08c4bdf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab20d7be8c5dd6ca941862eb1ff40289d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#gab20d7be8c5dd6ca941862eb1ff40289d">XIPIPSU_IER_OFFSET</a>&#160;&#160;&#160;0x18U</td></tr>
<tr class="memdesc:gab20d7be8c5dd6ca941862eb1ff40289d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset for Interrupt Enable Register.  <a href="group__ipipsu__api.html#gab20d7be8c5dd6ca941862eb1ff40289d">More...</a><br/></td></tr>
<tr class="separator:gab20d7be8c5dd6ca941862eb1ff40289d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga81c99cede6902a231b207281d9a6e212"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#ga81c99cede6902a231b207281d9a6e212">XIPIPSU_IDR_OFFSET</a>&#160;&#160;&#160;0x1CU</td></tr>
<tr class="memdesc:ga81c99cede6902a231b207281d9a6e212"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset for Interrupt Disable Register.  <a href="group__ipipsu__api.html#ga81c99cede6902a231b207281d9a6e212">More...</a><br/></td></tr>
<tr class="separator:ga81c99cede6902a231b207281d9a6e212"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6625ac1f3ce4297feacf81cd25acf53f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#ga6625ac1f3ce4297feacf81cd25acf53f">XIPIPSU_ECC_UE_MASK</a>&#160;&#160;&#160;0x40U</td></tr>
<tr class="memdesc:ga6625ac1f3ce4297feacf81cd25acf53f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Uncorrecteble Error mask.  <a href="group__ipipsu__api.html#ga6625ac1f3ce4297feacf81cd25acf53f">More...</a><br/></td></tr>
<tr class="separator:ga6625ac1f3ce4297feacf81cd25acf53f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga708ab6017d3971d9f9c0bf052fcdfd2f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__ipipsu__api.html#ga708ab6017d3971d9f9c0bf052fcdfd2f">XIPIPSU_ALL_MASK</a>&#160;&#160;&#160;0x0F0F0301U</td></tr>
<tr class="memdesc:ga708ab6017d3971d9f9c0bf052fcdfd2f"><td class="mdescLeft">&#160;</td><td class="mdescRight">All valid bit mask.  <a href="group__ipipsu__api.html#ga708ab6017d3971d9f9c0bf052fcdfd2f">More...</a><br/></td></tr>
<tr class="separator:ga708ab6017d3971d9f9c0bf052fcdfd2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
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